Subject: IEEE TCCA Email Monthly Sender: owner-tcca@ele.uri.edu Reply-To: tcca@ele.uri.edu Welcome to IEEE TCCA Email-Monthly, April 2003: 1. PACT03: 12th International Conference on Parallel Architectures and=20 Compilation Techniques,=20 Submitted by: David Kaeli kaeli@ece.neu.edu Call For Papers: URL: www.pactconf.org 2. PACT 2003 Workshops: Submitted by: Dieter Kranzlmueller, Website: http://www.ccs.neu.edu/pact03/ -> Workshops =09 3. HiPC 2003: 10th International Conference on High Performance Computing= =20 Submitted by: Yuanyuan Yang =20 =09 Website: http://www.hipc.org =20 4. IEEE Computer Special Issue on Power- and Temperature-Aware Computing=20 Submitted by: Kevin Skadron 5. Computer Architecture Letters =20 Submitted by: Kevin Skadron Website: * Archive: http://www.ele.uri.edu/tcca * To submit an email message to be distributed among TCCA members,=20 send an email to qyang@ele.uri.edu * To subscribe to this mailing list, please sign up at * To unsubscribe yourself from this mailing list: email to tcca-request@ele.uri.edu with message body: unsubscribe=20 ----------------------------------------------------------------------- Qing (Ken) Yang, Professor =09 Distinguished Engineering Professor e-mail: qyang@ele.uri.edu =20 Dept. of Electr. & Comput. Engineering Tel. (401) 874-5880 =20 University of Rhode Island Fax (401) 782-6422 =20 Kingston RI. 02881 http://www.ele.uri.edu/~qyang = =20 ------------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~Message Details~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ***************************************************************** PACT'03 12th International Conference on Parallel Architectures and Compilation Techniques September 27 - October 1, 2003 Chateau Sonesta Hotel, New Orleans, LA http://www.pactconf.org ***************************************************************** PACT-03 will be held in New Orleans, LA, a major cultural center of the southern United States. The city offers such attractions as Mardi Gras, the French Quarter, Bourbon St., the Mississippi River and is the home of dixieland jazz. PACT is a multi-disciplinary conference that brings together researchers from the hardware and software areas to present ground-breaking research related to parallel systems ranging across instruction-level parallelism, thread-level parallelism, multiprocessor parallelism and distributed systems. PACT solicits papers on advances in architecture, compilers, languages an= d applications across a broad range of topics, including, but not limited t= o: - Hardware/software optimizations for memory hierarchies - Programming languages for parallel scientific and object-oriented applications - Superscalar, VLIW, and multithreading architectures - I/O, network processing and O/S issues for parallel computing - Parallel aspects of power-aware and mobile/wireless computing - Reconfigurable computing and novel parallel architectures - Just-in-time/dynamic compilation for parallelism - Parallel algorithms, computation models and simulation techniques - Parallel software development tools supporting performance analysis/tun= ing and debugging Selected papers will be invited for publication in the Journal of Instruction Level Parallelism. Please check the following web site for paper submission information: http://www.pactconf.org *********************************************** Important Deadlines Abstract Submission Deadline: April 4, 2003 Full Paper Submission Deadline: April 11, 2003 Author Notification: June 20, 2003 Final Papers Due: July 18, 2003 *********************************************** General Chairs David Kaeli, Northeastern University David Koppelman, LSU Program Chairs Mary Hall, USC/ISI Vivek Sarkar, IBM Local Arrangements J. Ramanujam, LSU Finance Chair Nikos Pitsianis, Duke University Registration Chair Diana Keen, Cal Poly Tutorial Chair Csaba Andras Moritz, U. of Massachusetts Workshop Chair Martin Schulz, Cornell University Publications Chair Bruce Childers, University of Pittsburgh Publicity Chair Dieter Kranzlmueller, Kepler University Website Chair Gene Cooperman, Northeastern University Josep Llosa, UPC Barcelona Travel Awards Chair Lizy John, University of Texas, Austin ---------------- -------------------------------------------------------------------------= --- ---------------- Call for Papers: PACT 2003 Workshops: - AGridM 2003: Adaptive Grid Middleware - MEDEA 2003: Memory Access Decoupled Architectures and Related Issues - SNAPI 2003: Storage Network Architecture and Parallel I/Os - SPDSEC 2003: Hardware/Software Support for Parallel and Distributed Scientific and Engineering Computing Submission Deadline: June 16, 2003 -------------------------------------------------------------------------= --- ---------------- PACT 2003 Workshops The following workshops will be held together with PACT: - AGridM 2003: Workshop on Adaptive Grid Middleware - MEDEA 2003: Workshop on Memory Access Decoupled Architectures and Related Issues - SNAPI 2003: Workshop on Storage Network Architecture and Parallel I/Os - SPDSEC 2003: Workshop on Hardware/Software Support for Parallel and Distributed Scientific and Engineering Computing All workshops follow the following schedules: Submission Deadline: June 16, 2003 Author Notification: July 14, 2003 Final Papers Due: September 1, 2003 For submission procedures and special announcements, please check the individual workshop webpages for specific information. For general questions about workshops at PACT or to propose additional workshops, please contact the workshop chair Martin Schulz (schulz@csl.cornell.edu). Please also check: http://www.ccs.neu.edu/pact03/ -> Workshops -------------------------------------------------------------------------= --- ---- AGridM 2003: Workshop on Adaptive Grid Middleware Organizers: Wilson Rivera and Jaime Seguel, University of Puerto Rico Mayaguez, USA Scope: Grid computing research focuses on building a large-scale computing infrastructure by linking computing facilities at many distributed locations. By analogy with the electric power Grids, such systems are known as computational Grids. Significant effort has been spent in the design and implementation of middleware software for enabling computational Grids. These software packages have been successfully deployed and it is now possible to build clusters beyond the boundaries of a single local area network. However, the challenging problem of dynamically allocating resources in response to application requests for computational services remains unsolved. Adaptive middleware is software that resides between the application and the computer operating system and enables an application to adapt to changing availability of computing and networking resources. The purpose of this workshop is to provide an open forum for researchers from hardware and software areas to present, discuss, and exchange research-related ideas, results, and experiences in the area of adaptive middleware for computational Grids. Workshop webpage: http://ece.uprm.edu/agridm2003 -------------------------------------------------------------------------= --- ---- MEDEA 2003: Workshop on Memory Access Decoupled Architectures and Related Issues Organizers: Sandro Bartolini, University of Siena, Italy Pierfrancesco Foglia and Cosimo Antonio Prete, University of Pisa, Italy Scope: MEDEA-2003 aims to continue the high level of interest in the first three MEDEA Workshops held with PACT'00, PACT'01 and PACT'02. Due to the ever-increasing gap between CPU and memory speed, there is a great interest in evaluating and proposing processor, multiprocessor and system architectures dealing with the "memory wall" problem. In this scenario, memory performance issues can be better addressed when consider= ing system architecture and application domain in a joint manner. In fact, it is the combined effect of the applications and the system on which they are executing that stresses the memory subsystem and pushes towards speci= fic solutions. Typical architectural choices include single processor vs. multiprocessor solutions, single chip vs. COTS design, superscalar, multithreaded or VLIW architectures. Application domains encompass commercial (Web, DB, e-business, and multimedia), embedded (personal, mobile, automotive, automation and medical), networking applications, etc. The MEDEA-2003 Workshop wants to be a forum for academic and industrial people to meet, discuss and exchange their ideas and experience on the design and evaluation of architectures for embedded, commercial and general purpose systems. Main topics are memory performance issues and olutions in the various application domains. Workshop webpage: http://garga.iet.unipi.it/medea03/ -------------------------------------------------------------------------= --- ---- SNAPI 2003: Workshop on Storage Network Architecture and Parallel I/Os Organizer: Qing (Ken) Yang, University of Rhode Island, USA Scope: Data are the "life-blood" of computing and the main asset of any organization. Therefore, disk I/O and data storage on which data reside are becoming "first class citizens" in today's information world. This workshop intends to br= ing together researchers and practitioners from academia and industry to disc= uss cutting edge research on parallel and distributed data storage technologi= es. By discussing ongoing research, the workshop will expose participants to = the most recent developments in storage network architectures and parallel I/= O. Workshop webpage: http://www.ele.uri.edu/tcca/SNAPI_CFP.html -------------------------------------------------------------------------= --- ---- SPDSEC 2003: Workshop on Hardware/Software Support for Parallel and Distributed Scientific and Engineering Computing Organizers: Minyi Guo, University of Aizu, Japan Laurence Tianruo Yang, Francis Xavier University, Canada Scope: The field of parallel and distributed processing has obtained prominence through advances in electronic and integrated technologies beginning in the 1940s. Current times are very exciting and the years to come will witness a proliferation in the use of parallel and distributed systems, or supercomputers. The scientific and engineering application domains have a key role in shaping future research and development activities in academia and industry. The purpose of this workshop is to provide an open forum for computer scientists, computational scientists and engineers, applied mathematician= s, and researchers to present, discuss, and exchange research-related ideas, results, works-in-progress, and experiences in the areas of architectural= , compilation, and language support for problems in science and engineering applications. Workshop webpage: http://juliet.stfx.ca/people/fac/lyang/pact03-spdsec/ =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D *************************************************************************= **** * C A L L F O R P A R T I C I P A T I O N * * * * * * HiPC 2003 * * * * 10th International Conference on High Performance Computing *=20 * * * *=20 * http://www.hipc.org * * * * Submission Deadline: May 02, 2003 * * * *************************************************************************= **** HiPC 2003 December 17-20, 2003 Hyderabad, India The 10th Annual International Conference on High Performance Computing (H= iPC 2003) will be held in Hyderabad, an emerging center for Information Technology = in India, during December 17-20, 2003. It will serve as a forum to present current = work by researchers from around the world as well as highlight activities in Asia= in the high performance computing area. The conference has a history of attracti= ng participation from reputed researchers from all over the world. The ninth meeting held in Bangalore, India, in 2002 had 57 contributed pa= pers that were selected from 145 submissions from 12 countries, and additional spec= ial sessions. The conference had tutorials on cutting edge topics in high per= formance computing and related areas by leading researchers from academia and indu= stry. The 8th HiPC Conference (HiPC 2001) held in Hyderabad, India, in December= 2001, had 29 contributed papers that were selected from 108 submissions from 18 countries and approximately 220 participants attended the meeting. Please= refer to the website http://www.hipc.org for more information on previous meeti= ngs. Hyderabad, known as the City of Pearls, is the fifth largest metropolitan= city in India and is fast emerging as the hub of Information Technology. Many multi-national companies including Microsoft, Motorola, Oracle, GE Capita= l, IBM, among others have set up development units in Hyderabad. It is home to pr= emier universities such as International Institute of Information Technology an= d Indian School of Business and also some of the oldest and prestigious universiti= es in India including Osmania University and Jawaharlal Nehru Technical Univers= ity. Hyderabad is highly cosmopolitan and presents a mix of various cultures w= hich is reflected in its ethnic, cultural, architectural, and culinary diversity.= Details on local accommodations as well as travel tips will be posted on the Web = by August 2003, so you are encouraged to regularly check the HiPC Web site a= t www.hipc.org for updates. HiPC 2003 will emphasize the design and analysis of high performance comp= uting and networking systems and their scientific, engineering, and commercial appl= ications. In addition to technical sessions of contributed paper presentations, the= conference will offer invited presentations, a poster/presentation session, tutorial= s, vendor presentations, and exhibits. COSPONSORED BY International Institute of Information Technology, Hyderabad IEEE Computer Society Technical Committee on Parallel Processing ACM SIGARCH European Association for Theoretical Computer Science IFIP Working Group on Concurrent Systems National Association of Software and Service Companies (NASSCOM) Manufacturers Association for Information Technology (MAIT)=20 HELD IN CO-OPERATION WITH Indian Institutes of Technology Software Technology Parks of India Tata Institute of Fundamental Research, India Centre for Artificial Intelligence Research (CAIR), India CSIR Centre for Mathematical Modeling and Computer Simulation, India MEETING INFORMATION =20 The advance program will be available in July 2003. Check www.hipc.org fo= r updated information. IMPORTANT DATES=20 May 2, 2003 Conference Paper Due=20 May 6, 2003 Workshop Proposal Due=20 May 15, 2003 Tutorial Proposal Due=20 July 10, 2003 Notification of Acceptance/Rejection=20 August 15, 2003 Camera-Ready Paper Due=20 October 2, 2003 Poster/Presentation Summary Due -------------------------------------------------------------------------= ---- =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D CALL FOR PARTICIPATION =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D CALL FOR PAPERS=20 Authors are invited to submit original unpublished manuscripts that demon= strate current research in all areas of high performance computing including des= ign and analysis of parallel and distributed systems, embedded systems, and their applications in scientific, engineering, and commercial areas. Topic area= s of interest include but are not limited to: * Wireless and Mobile Computing * Parallel and Distributed C= omputing * Communication Networks and Sensor Networks * Heterogeneous Computing * Web-based Meta/Grid/P2P Computing * Network- and Cluster-based= Computing * Scalable Servers and System Area Networks * Embedded Applications and = Systems * Scientific/Engineering Applications * Network Processor and Rout= er Architectures * Commercial Applications and Workloads * Scalable and Latency-toler= ant Algorithms * High-speed Networks and Interconnection * Parallel Languages and Pro= gramming Networks Environments * Power-Efficient and Reconfigurable * EPIC Compilers and Softwar= e Support Architectures for ILP and TLP * Superscalar, Speculative, VLIW, and * Operating Systems for Scal= able and SMT Microarchitectures High-performance Computing * Compiler Technology for Power-aware and High-performance Computing Submitted manuscripts may not exceed 15 double-spaced pages of text using= 12 point size type on 8.5 x 11 inch pages with margins of at least 1 inch on each = of the four sides. References, figures, tables, etc. may be included in addition= to the fifteen pages of text. Authors should submit a correct PostScript (level = 2) file of their paper to be considered and make sure that the PostScript file wi= ll print on a PostScript printer that uses 8.5 x 11 inch size (letter size) paper.= The official language of the meeting is English. Manuscript submission procedures are available over the Web at http://www= .hipc.org. Electronic submissions must be in the form of a readable postscript file.= Authors unable to submit over the web can send an e-mail message to hipc2003@usc.= edu containing the following header information in ASCII form: title, author = name(s) and affiliation, abstract, keywords or topic area, postal address, e-mail= address, and telephone and fax numbers. The header (in ASCII) should be followed b= y the PostScript version of the complete manuscript (including title, author na= mes, affiliation, and abstract). The subject line of the email should include = either one of the topic areas for the paper as given above or 5-10 keywords for = the paper. Hard copy submissions are permitted but electronic submissions are strong= ly encouraged. Like electronic submissions, hard copy submissions must be re= ceived by May 2, 2003. Please send six copies of the manuscript to the Program C= hair. Fax submissions will not be considered. Manuscripts must be received by May 2, 2003. All manuscripts will be revi= ewed. Submitted papers must not be currently under review for any other publica= tion. Submissions received after the due date or exceeding the length limit may= not be considered. Notification of review decisions will be mailed by July 10, 2= 003. Camera-ready papers are due August 15, 2003. Proceedings will be availabl= e at the conference and also on the Web after the conference. Selected papers will be considered for publication in a special issue of = IEEE Transactions on Computers to be published in 2004. PROGRAM CHAIR =20 Timothy Pinkston, University of Southern California Department of EE-Systems 3740, McClintock Ave., EEB 208 University of Southern California Los Angeles, CA 90089, USA Internet: tpink@charity.usc.edu PROGRAM VICE CHAIRS=20 Algorithms Yuanyuan Yang, State University of New York at Stony Brook Applications Xiaodong Zhang, National Science Foundation Architecture Rajiv Gupta, University of Arizona Communication Networks Stephan Olariu, Old Dominion University Systems Software Jos=E9 E. Moreira, IBM T.J. Watson Research Center PROGRAM COMMITTEE Algorithms: Mikhail Atallah, Purdue University Michael A. Bender, State University of New York at Stony= Brook Xiaotie Deng, City University of Hong Kong Ding-Zhu Du, National Science Foundation Qianping Gu, Simon Fraser University Hong Jiang, University of Nebraska-Lincoln Ran Libeskind-Hadas, Harvey Mudd College Koji Nakano, Japan Advanced Institute of Science and Tec= hnology Yavuz Oruc, University of Maryland at College Park Arnold L. Rosenberg, University of Massachusetts at Amhe= rst Christian Scheideler, Johns Hopkins University Jinwoo Suh, University of Southern California/ISI Albert Y. Zomaya, University of Sydney Applications: Srinivas Aluru, Iowa State University Randall Bramley, Indiana University Jack Dongarra, University of Tennessee Craig Douglas, University of Kentucky and Yale Universit= y Ananth Grama, Purdue University David Keyes, Old Dominion University Xiaoye Li, Lawrence Berkeley National Laboratory Aiichiro Nakano, University of Southern California P.J. Narayanan, Intl. Institute of Information Technolog= y, Hyderabad Yousef Saad, University of Minnesota Eric de Sturler, University of Illinois at Urbana-Champa= ign Xian-He Sun, Illinois Insitute of Technology Xiaoge Wang, Tsinghua Unviersity Li Xiao, Michigan State University Architecture: Prith Banerjee, Northwestern University Sandhya Dwarkadas, University of Rochester Manoj Franklin, University of Maryland Kanad Ghose, Binghamton University, State University of = New York Daniel Jimenez, Rutgers University Mahmut Kandemir, Pennsylvania State University Olav Lysne, University of Oslo Avi Mendelson, Intel, Israel Dhabaleswar Panda, Ohio State University Fabrizio Petrini, Los Alamos National Laboratory Antonio Robles, Polytechnic University of Valencia Andre Seznec, IRISA, France Per Stenstrom, Chalmers University of Technology David Whalley, Florida State University Jun Yang, University of California, Riverside Communication Marco Conti, CNUCE/CNR Pisa Networks: Abhay Karandikar, Indian Institute of Technology, Bombay Victor Leung, University of British Columbia Cauligi Raghavendra, University of Southern California Dheeraj Sanghi, Indian Institute of Technology, Kanpur Pradip Srimani, Clemson University Mani Srivastava, University of California, Los Angeles Ivan Stojmenovic, University of Ottawa Jie Wu, Florida Atlantic University Jingyuan Zhang, University of Alabama Albert Y. Zomaya, University of Sydney Systems Gianfranco Bilardi, University of Padova Softare: Rahul Garg, IBM India Research Laboratory Hironori Kasahara, Waseda University Barney Maccabe, University of New Mexico Rajib Mall, Indian Institute of Technology, Kharagpur Sam Midkiff, Purdue University Edson Midorikawa, University of Sao Paulo Michael Phillipsen, Friedrich-Alexander-University Lawrence Rauchwerger, Texas A&M University Dilma Da Silva, IBM T.J. Watson Research Center Anand Sivasubramaniam, Pennsylvania State University Yanyong Zhang, Rutgers University BEST PAPER AWARDS=20 These awards, sponsored by Infosys, will be awarded to outstanding contri= buted papers in the areas of Systems and Algorithms and Applications.=20 AWARDS CHAIR=20 Arvind, MIT=20 WORKSHOPS=20 Proposals are solicited for workshops to be held in conjunction with the = main conference. Interested individuals should submit a proposal by May 06, 20= 03 to the Workshops Chair. For additional details and submission procedure v= isit http://www.hipc.org/hipc2003. WORKSHOPS CHAIR C. P. Ravikumar, Texas Instruments India Internet: ravikumar@india.ti.com POSTER/PRESENTATION SESSION=20 In addition to the contributed papers session, a plenary poster/presentat= ion session emphasizing novel applications of high performance computing is p= lanned. It will offer brief presentation time for each poster and will be followe= d by a "walk-up and talk" setting. To be considered, send a 5 page summary of yo= ur work to the Poster/Presentation Chair by October 2, 2003. For additional = details contact the Poster/Presentation Chair. POSTER/PRESENTATION CHAIR Rajkumar Buyya, The University of Melbourne Internet: rajkumar@buyya.com TUTORIALS=20 Proposals are solicited for tutorials to be held at the meeting. Interest= ed individuals should submit a proposal by May 15, 2003 to the Tutorials Cha= ir. The proposal should include a brief description of the intended audience,= a lecture outline, and a vita for each lecturer. TUTORIALS CHAIR Srinivas Aluru, Iowa State University Internet: aluru@iastate.edu EXHIBITS/VENDORS PRESENTATIONS Companies and R&D laboratories are encouraged to present their exhibits a= t the meeting. In addition, a full day of vendor presentations is planned. For = details, visit www.hipc.org/hipc2003. -------------------------------------------------------------------------= ---- =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D HiPC 2003 ORGANIZATION =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D GENERAL CO-CHAIRS Viktor K. Prasanna, University of Southern California M. Vidyasagar, Tata Consultancy Services VICE GENERAL CHAIR David A. Bader, University of New Mexico PROGRAM CHAIR Timothy Pinkston, University of Southern California STEERING CHAIR Viktor K. Prasanna, University of Southern California WORKSHOPS CHAIR C.P. Ravikumar, Texas Instruments India POSTER/PRESENTATION CHAIR Rajkumar Buyya, The University of Melbourne SCHOLARSHIPS CHAIR Dheeraj Sanghi, Indian Institute of Technology, Kanpur FINANCE CO-CHAIRS A.K.P. Nambiar, Software Technology Park, Bangalore Ajay Gupta, Western Michigan University TUTORIALS CHAIR Srinivas Aluru, Iowa State University AWARDS CHAIR Arvind, MIT KEYNOTE CHAIR Rajesh Gupta, University of California, San Diego PUBLICITY CHAIR Manish Parashar, Rutgers, The State University of New Jersey STEERING COMMITTEE Jose Duato, Universidad Politecnica de Valencia, Spain Viktor K. Prasanna, University of Southern California, Chair N. Radhakrishnan, US Army Research Lab Sartaj Sahni, University of Florida Assaf Schuster, Technion, Israel Institute of Technology, Israel Steering Committee 2003 membership also includes the general co-chairs, p= rogram chairs, and vice general chairs from 2002, 2003, & 2004. =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D ---- IEEE Computer Special Issue on Power- and Temperature-Aware Computing=20 Guest Editors: Mircea R. Stan, ECE Department, University of Virginia Kevin Skadron, CS Department, University of Virginia =20 Call for Papers: deadline June 1, 2003 Despite the continuous scaling of processes and supply voltages, and the increased awareness of low-power issues in the computer design and design automation communities, power consumption by state-of-the-art ICs has continually increased in recent years. This apparent paradox results from the increased density enabled by process scaling and a multilayer interconnect, coupled with increases in area and especially in clock frequency driven by an insatiable market for high performance systems. Temperature is also on the verge of becoming a first-class design constraint along with the more traditional constraints of cost, performance, and power. The increasing importance of thermal effects stems from an exponential increase in on-chip power densities, with today's processors having power densities greater than a hot plate and within an order of magnitude of a rocket nozzle. An integrated and coordinated set of design techniques is required in order to successfully manage growing power and thermal demands while still meeting performance, reliability, and cost targets.=20 Research, characterization, and survery papers are requested for the December 2003 issue of IEEE Computer. This issue will be devoted to the subjects of Power-Aware and Temperature-Aware Computing, including run-time and compile-time techniques at the circuit, architecture, and system levels for improving battery life, current delivery, and operating temperature; and integrated concerns of reliability and quality of service. An integrated and coordinated set of design techniques is required in order to successfully manage growing power and thermal demands while still meeting performance, reliability, and cost targets. Example topics of interest include circuit, architecture, and system techniques for regulating static and dynamic power; improved models for power, current-delivery, and thermal aspects; compiler-hardware and OS-hardware cooperation, methods for optimizing energy efficiency subject to real-time or quality-of-service requirements, and active-cooling techniques.=20 Send inquiries to Guest Editors Mircea R. Stan, University of Virginia (mircea@virginia.edu) and Kevin Skadron, University of Virginia (skadron@virginia.edu). Submit pdf documents by June 1 to computer-ma@computer.org and specify the special issue of Power-Aware and Temperature-Aware Computing. =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D Computer Architecture Letters is pleased to announce the publication of another paper online at our website, ; the abstract appears below. The papers will appear in print in our next paper issue. The print issues are distributed to the entire IEEE Computer Society TCCA membership, and e-mail notifications of newly accepted papers are sent on a regular basis to the TCCA and ACM SIGARCH memberships. The objective of Letters is to publish short (4-page), timely articles of high-quality work. We are very much aware of the long delays in our field between submissions of manuscripts and their eventual appearance in print. We are doing something about that with this journal. After a little more than one year of operation, we have maintained an average turnaround time from submission to author notification of just one month, with an acceptance rate of 20%. We encourage the community to continue submitting papers to Letters.=20 Submissions are welcomed on any topic in computer architecture, especially but not limited to:=20 - Microprocessor and multiprocessor systems=20 - Microarchitecture and ILP processors=20 - Workload characterization=20 - Performance evaluation and simulation techniques=20 - Compiler-hardware and operating system-hardware interactions=20 - Interconnect architectures=20 - Memory and cache systems=20 - Power and thermal issues at the architecture level=20 - I/O architectures and techniques=20 - Independent validation of previously published results=20 - Analysis of unsuccessful techniques=20 - Network and embedded-systems processors=20 - Real-time and high-availability architectures=20 - Reconfigurable systems=20 The call for papers and instructions for submission can be found at Abstracts --------- K.-H. Sihn, J. Lee, J.-W. Cho. "A Speculative Coherence Scheme using Decoupling Synchronization for Multiprocessor Systems." Volume 2, Mar. 2003.=20 Abstract: This paper proposes a new speculative coherence scheme, SCDS, for hardware distributed shared memory systems to reduce the overhead of coherence action in directory-based cache-coherence protocol. SCDS has two main features, predicting accurate timing of speculative coherence with synchronization information and detecting write pattern (migratory and non-migratory) for exclusive blocks' speculative coherence action. In our simulation, SCDS outperforms existing schemes (DSI and LTP) for well-synchronized applications. =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D -------------------------------------------------------------------------= - * To unsubscribe yourself from this mailing list: email to tcca-request@ele.uri.edu with message body: unsubscribe=20